Design automation for deterministic lateral displacement by leveraging deep Q-network DOI
Yu‐Wei Chen, Yidan Zhang, Junchao Wang

и другие.

Biomicrofluidics, Год журнала: 2025, Номер 19(2)

Опубликована: Март 1, 2025

Despite the widespread application of microfluidic chips in research fields, such as cell biology, molecular chemistry, and life sciences, process designing new for specific applications remains complex time-consuming, often relying on experts. To accelerate development high-performance high-throughput chips, this paper proposes an automated Deterministic Lateral Displacement (DLD) chip design algorithm based reinforcement learning. The proposed treats throughput sorting efficiency DLD key optimization objectives, achieving multi-objective optimization. integrates existing results from our team, enabling rapid evaluation scoring parameters. Using comprehensive performance system deep Q-network technology, can balance optimal separation high chips. Additionally, quick execution capability effectively guides engineers developing during phase.

Язык: Английский

Design automation for deterministic lateral displacement by leveraging deep Q-network DOI
Yu‐Wei Chen, Yidan Zhang, Junchao Wang

и другие.

Biomicrofluidics, Год журнала: 2025, Номер 19(2)

Опубликована: Март 1, 2025

Despite the widespread application of microfluidic chips in research fields, such as cell biology, molecular chemistry, and life sciences, process designing new for specific applications remains complex time-consuming, often relying on experts. To accelerate development high-performance high-throughput chips, this paper proposes an automated Deterministic Lateral Displacement (DLD) chip design algorithm based reinforcement learning. The proposed treats throughput sorting efficiency DLD key optimization objectives, achieving multi-objective optimization. integrates existing results from our team, enabling rapid evaluation scoring parameters. Using comprehensive performance system deep Q-network technology, can balance optimal separation high chips. Additionally, quick execution capability effectively guides engineers developing during phase.

Язык: Английский

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