Journal of Low Power Electronics and Applications, Год журнала: 2024, Номер 14(3), С. 45 - 45
Опубликована: Сен. 4, 2024
A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach verified with prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves measured DC gain of 105 V/V, differential AC 40.3 dB bandwidth 55 kHz, CMRR approximately 75 dB, and PSRR dB. input-referred noise 7 nV/√Hz 923 nVrms integrated from 100 Hz 10 resulting Noise Efficiency Factor (NEF) 2.84 Power (PEF) 18.3. configuration by nearly 25% full voltage supply maintains small area design. Action potentials medial giant fiber an earthworm are recorded as example application.
Язык: Английский