Bulletin of the National Research Centre/Bulletin of the National Research Center, Год журнала: 2023, Номер 47(1)

Опубликована: Июнь 30, 2023

Abstract Background MathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing quick proof of concept on the one hand g easy-to-use platform testing verification other. It main drawbacks over these advantages; it generates code that is not optimized both area frequency. Results In this paper, we provide technique optimizing frequency without losing advantages. The most affecting problem found loops. This paper classifies loop writing purposes into two types. first preferable introduces ease few lines instead repeating code. second type intended to solve. Type II appearing when algorithm should perform several clock cycles. Writing traditionally, force synthesizer implement all repetitive cycles as hardware be done in cycle. cycle wide time slow optimization problem. We compare before after implementation our proposed technique. Conclusions used Xilinx Spartan 6 XC6SLX4-2CPG196 FPGA. Our improves number slice LUTs (Look Up Tables) requirement from 366 72%. improved from: 26.574 185.355 MHz. Based that, now recommend using FPGA Design.

Язык: Английский