An optimizing technique for using MATLAB HDL coder DOI Creative Commons
Somaya Kayed, Ghada Elsayed

Bulletin of the National Research Centre/Bulletin of the National Research Center, Journal Year: 2023, Volume and Issue: 47(1)

Published: June 30, 2023

Abstract Background MathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing quick proof of concept on the one hand g easy-to-use platform testing verification other. It main drawbacks over these advantages; it generates code that is not optimized both area frequency. Results In this paper, we provide technique optimizing frequency without losing advantages. The most affecting problem found loops. This paper classifies loop writing purposes into two types. first preferable introduces ease few lines instead repeating code. second type intended to solve. Type II appearing when algorithm should perform several clock cycles. Writing traditionally, force synthesizer implement all repetitive cycles as hardware be done in cycle. cycle wide time slow optimization problem. We compare before after implementation our proposed technique. Conclusions used Xilinx Spartan 6 XC6SLX4-2CPG196 FPGA. Our improves number slice LUTs (Look Up Tables) requirement from 366 72%. improved from: 26.574 185.355 MHz. Based that, now recommend using FPGA Design.

Language: Английский

Gas Classification System Based on Hybrid Waveform Modulation Technology on FPGA DOI
Jiade Zhang, Mingzhi Jiao, Lei Duan

et al.

Sensors and Actuators B Chemical, Journal Year: 2025, Volume and Issue: unknown, P. 137637 - 137637

Published: March 1, 2025

Language: Английский

Citations

0
Comparative study of respiratory sounds classification methods based on cepstral analysis and artificial neural networks DOI
Abdelkrim Semmad, Mohammed Bahoura

Computers in Biology and Medicine, Journal Year: 2024, Volume and Issue: 171, P. 108190 - 108190

Published: Feb. 20, 2024

Language: Английский

Citations

3
Machine Learning Approach for Predicting Hydrothermal Liquefaction of Lignocellulosic Biomass DOI
Tossapon Katongtung,

Sanphawat Phromphithak,

Thossaporn Onsree

et al.

BioEnergy Research, Journal Year: 2024, Volume and Issue: 17(4), P. 2246 - 2258

Published: May 24, 2024

Language: Английский

Citations

3
Research on the application of knowledge mapping and knowledge structure construction based on adaptive learning model DOI

Xiyin Zeng,

Shouqiang Liu

Expert Systems with Applications, Journal Year: 2024, Volume and Issue: 249, P. 123400 - 123400

Published: Feb. 17, 2024

Language: Английский

Citations

2
An optimizing technique for using MATLAB HDL coder DOI Creative Commons
Somaya Kayed, Ghada Elsayed

Bulletin of the National Research Centre/Bulletin of the National Research Center, Journal Year: 2023, Volume and Issue: 47(1)

Published: June 30, 2023

Abstract Background MathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing quick proof of concept on the one hand g easy-to-use platform testing verification other. It main drawbacks over these advantages; it generates code that is not optimized both area frequency. Results In this paper, we provide technique optimizing frequency without losing advantages. The most affecting problem found loops. This paper classifies loop writing purposes into two types. first preferable introduces ease few lines instead repeating code. second type intended to solve. Type II appearing when algorithm should perform several clock cycles. Writing traditionally, force synthesizer implement all repetitive cycles as hardware be done in cycle. cycle wide time slow optimization problem. We compare before after implementation our proposed technique. Conclusions used Xilinx Spartan 6 XC6SLX4-2CPG196 FPGA. Our improves number slice LUTs (Look Up Tables) requirement from 366 72%. improved from: 26.574 185.355 MHz. Based that, now recommend using FPGA Design.

Language: Английский

Citations

3