Memristor Crossbar Array with Enhanced Device Yield for In-Memory Vector–Matrix Multiplication

ACS Applied Electronic Materials, Journal Year: 2024, Volume and Issue: 6(6), P. 4099 - 4107

Published: May 30, 2024

In this work, we present a fabrication strategy for high-yield memristor crossbar arrays. Our approach uses an Al2O3/TiOx-based bilayer with combination of dielectric and oxygen reservoir layer. The process is optimized by controlling the thickness Al2O3 layer to decrease forming voltage, thus reducing possibility device failure due excessive current during process. We also investigate yield trends concentration TiOx layer, achieving over 98% under optimal conditions. then fabricate array conditions statistically characterize devices in array. As compute-in-memory in-memory computing application, develop fully connected neural network 5 × image classification based on vector–matrix multiplication. By transferring pretrained error less than 5%, 100% accuracy can be experimentally achieved as result inference measurement 480 test images.

Language: Английский

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Memristive ternary Łukasiewicz logic based on reading-based ratioed resistive states (3R)

Philosophical Transactions of the Royal Society A Mathematical Physical and Engineering Sciences, Journal Year: 2025, Volume and Issue: 383(2288)

Published: Jan. 1, 2025

The thirst for more efficient computational paradigms has reignited interest in computation memory (CIM), a burgeoning topic that pivots on the strengths of versatile logic systems. Surging ahead this innovative milieu, multi-valued systems have been identified as possessing potential to amplify storage density and efficacy. Notably, ternary attracted widespread research owing its relatively lower complexity, offering promising alternative traditional binary computation. This study provides insight into feasibility CIM domain using resistive random-access (ReRAM) devices. Its multi-level programming capability making it an ideal conduit integration logic. We focus Łukasiewicz because characteristics are highly suitable mapping values with input output signals. approach is characterized by voltage-reading-based ease subsequent utilization validated 1T1R crossbar arrays integrated ReRAM chip (Memory Advanced Demonstrator 200 mm). In addition, effect variability memristive devices logical parallel operation also investigated. article part theme issue ‘Emerging technologies future secure computing platforms’.

Language: Английский

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A Fully Integrated Memristive Chaotic Circuit Based on Memristor Emulator with Voltage-Controlled Oscillator

Micromachines, Journal Year: 2025, Volume and Issue: 16(3), P. 246 - 246

Published: Feb. 21, 2025

This paper introduces a fully integrated memristive chaotic circuit, which is based on voltage-controlled oscillator (VCO). The circuit employs architecture that offers reduced power consumption and smaller footprint compared to the use of discrete components. Specifically, VCO utilized generate oscillatory signal, whereas memristor emulator serves as nonlinear element. constructed using single operational transconductance amplifier (OTA), two transistors, grounded capacitor. straightforward design contributes diminished usage within chip’s area. incorporates dual delay unit implements current compensation enhance oscillation frequency broaden VCO’s tunable range. Fabricated SMIC 180 nm CMOS process, this occupies mere 0.0072 mm2 chip area, demonstrating both efficient compact. Simulation outcomes indicate proposed capable operating at maximum 300 MHz. able produce signal with an ranging from 158 MHz 286 MHz, powered by supply 0.9 V, peak 3.5553 mW. Lyapunov exponent time series resultant spans 0.2572 0.4341.

Language: Английский

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A Novel Dynamic Clock Generator Circuit for the Threshold Logic Gate

Gazi University Journal of Science Part A Engineering and Innovation, Journal Year: 2025, Volume and Issue: 12(1), P. 61 - 71

Published: March 26, 2025

Threshold Logic Gate (TLG) has gained attention with the emergence of novel technologies such as memristors. TLG offers improved performance and lower power dissipation while occupying less silicon area. This paper introduces a dynamic clock generator circuit that further enhances performance. The proposed replaces NAND gate-based approach used for generation in differential implementations. It reduces propagation delay reducing its static dissipation, an important factor energy-efficient design. Simulations indicate up to 25% reduction compared approach. Furthermore, occupies 45% area than gate. These findings highlight potential advanced threshold logic implementations, paving way innovations field.

Language: Английский

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Hafnium oxide-based nonvolatile ferroelectric memcapacitor array for high energy-efficiency neuromorphic computing

Nano Energy, Journal Year: 2025, Volume and Issue: unknown, P. 111011 - 111011

Published: April 1, 2025

Language: Английский

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Physical mechanisms and integration design of memristors

Materials Today Nano, Journal Year: 2025, Volume and Issue: unknown, P. 100628 - 100628

Published: April 1, 2025

Language: Английский

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Synergistic enhancement of memristive behavior and self-rectifying effect in MnO2 based memristor by ions doping method

Applied Materials Today, Journal Year: 2025, Volume and Issue: 44, P. 102771 - 102771

Published: May 10, 2025

Language: Английский

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Configurable Kernel Map Implementation in Memristor Crossbar for Convolution Neural Network

Advanced Intelligent Systems, Journal Year: 2025, Volume and Issue: unknown

Published: May 15, 2025

This study experimentally verifies a configurable convolutional neural network implementation in 48 × memristor crossbar array. It allows the number of convolution reading cycles to be adjusted based on design demands, such as area or time constraints. adaptability can achieved by modifying kernel weights array, enabling balance between and efficiency. A detailed algorithm for scheme is presented, taking into account factors array size, feature map cycle limits. Also, experimental validation using binary 12 MNIST dataset demonstrates practical applicability our scheme. By varying per inference ( N ), this analyzes how different sizes affect performance, confirming relationship total cells cell ) cycles. Larger values result increased usage faulty devices, leading more distorted pixels. Additionally, it robustness weight errors, finding that longer are less robust due frequent reads critical fault devices within crossbar, causing accuracy degradation.

Language: Английский

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Wordline Input Bias Scheme for Neural Network Implementation in 3D-NAND Flash

Biomimetics, Journal Year: 2025, Volume and Issue: 10(5), P. 318 - 318

Published: May 15, 2025

In this study, we propose a neuromorphic computing system based on 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs). The approach leverages the velocity saturation effect in short-channel MOSFETs, which enables linear increase drain current with respect to gate voltage region. A NAND array TANOS (TiN/Al2O3/Si3N4/SiO2/poly-Si) stack was fabricated, and its electrical reliability characteristics were evaluated. Output of (L = 1 µm) long-channel 50 devices compared, confirming behavior due saturation. proposed system, WL serve as inputs, summed bitline (BL) currents represent outputs. Each synaptic weight is implemented using two paired devices, each layer corresponds fully connected (FC) layer, enabling efficient vector-matrix multiplication (VMM). MNIST pattern recognition conducted, demonstrated only 0.32% accuracy drop for device compared ideal case, 0.95% degradation under 0.5 V threshold variation, while maintaining robustness. These results highlight strong potential memory, offers high integration density technological maturity, applications.

Language: Английский

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Dynamic memristor array with multiple reservoir states for training efficient neuromorphic computing

Journal of Materials Chemistry C, Journal Year: 2024, Volume and Issue: 12(34), P. 13516 - 13524

Published: Jan. 1, 2024

Exploration of efficient neuromorphic computing using Pt/Al/TiO y /TiO x /Al 2 O 3 /Pt array memristors implemented a reservoir with 16 states, demonstrating the training process synaptic images.

Language: Английский

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