Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs DOI
Shams Ul Haq, Erfan Abbasian, Tabassum Khurshid

et al.

Physica Scripta, Journal Year: 2024, Volume and Issue: 99(8), P. 085237 - 085237

Published: July 19, 2024

Abstract Recently, carbon nanotube field-effect transistors (CNTFETs) have garnered significant attention from VLSI engineers due to their exceptional electrical properties. This paper proposes a novel high-speed, low-power eight-transistor (8 T) static random-access memory (SRAM) cell based on 32-nm CNTFET technology. The SRAM was simulated using the HSPICE tool with V DD of 0.9 V. high-speed and characteristics design are attributed high subthreshold slope carrier mobility metal-oxide-semiconductor transistor (MOSFET)-like CNTFETs utilized in simulations. implementation dual threshold transistors, coupled transmission gate for bitline access, contributes enhanced performance. Key performance metrics such as noise margins, power consumption, delay, quality metric (SEQM) proposed been evaluated compared existing CNTFET-based designs. demonstrates reductions 73.73%, 43.18%, 58.70% read power, write hold respectively, lowest respective values other examined ranks second, third, second margin (WSNM), (HSNM), (RSNM), among Additionally, exhibits least sensitivity parametric variations SEQM, which provides comprehensive assessment access times, usage cell, has calculated. SEQM is 10.6, 1.89, 13.15, 1.82 times higher than that C6T, BLP8T, Mani’s 10 T, LP8T, respectively.

Language: Английский

Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis DOI
Vipin Kumar Sharma, Abhishek Kumar

Journal of Electronic Testing, Journal Year: 2025, Volume and Issue: 41(1), P. 15 - 25

Published: Feb. 1, 2025

Language: Английский

Citations

0
Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology DOI
Shams Ul Haq, Erfan Abbasian, Tabassum Khurshid

et al.

Physica Scripta, Journal Year: 2024, Volume and Issue: 99(8), P. 085119 - 085119

Published: July 22, 2024

Abstract Multi-valued logic (MVL) extends binary by providing a framework to represent complex systems with more than two truth values. MVL was introduced confront the enormous interconnect issue associated in implementing presnt day nanoelectronic architectures. This paper delves into circuit design, computational aspects, and practical applications of quaternary system, which is type four The multi-threshold property carbon nanotube field-effect-transistors (CNTFETs), combined ability resistive random-access memory (RRAM) store multiple resistance values, has enabled design gates arithmetic circuits. A new CNTFET-based architecture been proposed implement compatible existing technologies. Quaternary such as inverter, NAND, NOR, circuits including decoder, half adder, multiplier have designed. power-delay-product (PDP) 62.38%, 93.4%, 80.29%, 14.79%, 20% less least PDP designs under consideration. static power reduction due effecciency high OFF state offered integrating RRAM explored.The subject various types parameter variations validate thir proper functionality presence these variations.

Language: Английский

Citations

3
Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs DOI
Shams Ul Haq, Erfan Abbasian, Tabassum Khurshid

et al.

Physica Scripta, Journal Year: 2024, Volume and Issue: 99(8), P. 085237 - 085237

Published: July 19, 2024

Abstract Recently, carbon nanotube field-effect transistors (CNTFETs) have garnered significant attention from VLSI engineers due to their exceptional electrical properties. This paper proposes a novel high-speed, low-power eight-transistor (8 T) static random-access memory (SRAM) cell based on 32-nm CNTFET technology. The SRAM was simulated using the HSPICE tool with V DD of 0.9 V. high-speed and characteristics design are attributed high subthreshold slope carrier mobility metal-oxide-semiconductor transistor (MOSFET)-like CNTFETs utilized in simulations. implementation dual threshold transistors, coupled transmission gate for bitline access, contributes enhanced performance. Key performance metrics such as noise margins, power consumption, delay, quality metric (SEQM) proposed been evaluated compared existing CNTFET-based designs. demonstrates reductions 73.73%, 43.18%, 58.70% read power, write hold respectively, lowest respective values other examined ranks second, third, second margin (WSNM), (HSNM), (RSNM), among Additionally, exhibits least sensitivity parametric variations SEQM, which provides comprehensive assessment access times, usage cell, has calculated. SEQM is 10.6, 1.89, 13.15, 1.82 times higher than that C6T, BLP8T, Mani’s 10 T, LP8T, respectively.

Language: Английский

Citations

2