A 4096 channel event-based multielectrode array with asynchronous outputs compatible with neuromorphic processors DOI Creative Commons
Matteo Cartiglia, Filippo Costa, Shyam Narayanan

et al.

Research Square (Research Square), Journal Year: 2023, Volume and Issue: unknown

Published: Oct. 25, 2023

Abstract Bio-signal sensing represents a pivotal domain in the medical applications of bioelectronics. Traditional methods have, so far, focused on capturing these signals as accurately possible, leading to high sampling rates clocked synchronous architectures. Given sparse activity bio-signals, this approach often results large amounts digitized data with no relevant information and significant amount energy consumed during transmission. Here, we introduce self-clocked microelectrode array (MEA) that senses digitizes bio-signals at pixel level by encoding their changes asynchronous digital address-events, significantly reducing needs be transmitted off-chip. This novel MEA comprises an 64 × electrodes, 2D-arbiter, Address-Event Representation (AER) communication block. Each within operates autonomously, monitoring input for relative voltage fluctuations instigated cellular activity. Upon detecting sufficiently signal change, produces pulse encoded its corresponding address. Positive are “up” events, while negative ones “down” events and, upon generation, routed off-chip instantly via arbiter. present from chip characterization experimental measurements using electrogenic cells. Moreover, interface mixed-signal neuromorphic processor, demonstrating prototype end-to-end event-based bio-signal processing.

Language: Английский

Neuromorphic computing at scale DOI
Dhireesha Kudithipudi, Catherine D. Schuman, Craig M. Vineyard

et al.

Nature, Journal Year: 2025, Volume and Issue: 637(8047), P. 801 - 812

Published: Jan. 22, 2025

Language: Английский

Citations

4
DenRAM: neuromorphic dendritic architecture with RRAM for efficient temporal processing with delays DOI Creative Commons
S. D’Agostino, Filippo Moro,

Tristan Torchet

et al.

Nature Communications, Journal Year: 2024, Volume and Issue: 15(1)

Published: April 24, 2024

An increasing number of studies are highlighting the importance spatial dendritic branching in pyramidal neurons neocortex for supporting non-linear computation through localized synaptic integration. In particular, branches play a key role temporal signal processing and feature detection. This is accomplished thanks to coincidence detection (CD) mechanisms enabled by presence delays that align temporally disparate inputs effective Computational on spiking neural networks further highlight significance achieving spatio-temporal pattern recognition with pure feed-forward networks, without need resorting recurrent architectures. this work, we present "DenRAM", first realization network compartments, implemented using analog electronic circuits integrated into 130 nm technology node coupled Resistive Random Access Memory (RRAM) technology. DenRAM's use RRAM devices implement both weights network. By configuring reproduce bio-realistic timescales, exploiting their heterogeneity experimentally demonstrate ability replicate delay profiles, efficiently CD recognition. To validate architecture, conduct comprehensive system-level simulations two representative benchmarks, demonstrating resilience hardware noise, its superior accuracy compared architectures an equivalent parameters. DenRAM not only brings rich capabilities neuromorphic architectures, but also reduces memory footprint edge devices, warrants high represents significant step-forward low-power real-time technologies.

Language: Английский

Citations

13
Robust compression and detection of epileptiform patterns in ECoG using a real-time spiking neural network hardware framework DOI Creative Commons
Filippo Costa, Eline Schaft, Geertjan Huiskamp

et al.

Nature Communications, Journal Year: 2024, Volume and Issue: 15(1)

Published: April 16, 2024

Abstract Interictal Epileptiform Discharges (IED) and High Frequency Oscillations (HFO) in intraoperative electrocorticography (ECoG) may guide the surgeon by delineating epileptogenic zone. We designed a modular spiking neural network (SNN) mixed-signal neuromorphic device to process ECoG real-time. exploit variability of inhomogeneous silicon neurons achieve efficient sparse decorrelated temporal signal encoding. interface full-custom SNN BCI2000 real-time framework configure setup detect HFO IED co-occurring with (IED-HFO). validate on pre-recorded data obtain rates that are concordant previously validated offline algorithm (Spearman’s ρ = 0.75, p 1e-4), achieving same postsurgical seizure freedom predictions for all patients. In remote on-line analysis, recorded Utrecht was compressed transferred Zurich processing successful IED-HFO detection These results further demonstrate how automated enable use clinical practice.

Language: Английский

Citations

6
Emerging Materials and Computing Paradigms for Temporal Signal Analysis DOI Open Access
Teng Zhang, Stanisław Woźniak, Syed Ghazi Sarwat

et al.

Advanced Materials, Journal Year: 2025, Volume and Issue: unknown

Published: Feb. 11, 2025

Abstract In the era of relentless data generation and dynamic information streams, demand for efficient robust temporal signal analysis has intensified across diverse domains such as healthcare, finance, telecommunications. This perspective study explores unfolding landscape emerging materials computing paradigms that are reshaping way signals analyzed interpreted. Traditional processing techniques often fall short when confronted with intricacies time‐varying data, prompting exploration innovative approaches. The rise devices empowers real‐time by in situ, mitigating latency concerns. Through this perspective, untapped potential is highlighted, offering valuable insights into both challenges opportunities. Standing on cusp a new computing, understanding harnessing these pivotal unraveling complexities embedded within dimensions propelling realms previously deemed inaccessible.

Language: Английский

Citations

0
The road to commercial success for neuromorphic technologies DOI Creative Commons
Dylan R. Muir, Sadique Sheik

Nature Communications, Journal Year: 2025, Volume and Issue: 16(1)

Published: April 15, 2025

Neuromorphic technologies adapt biological neural principles to synthesise high-efficiency computational devices, characterised by continuous real-time operation and sparse event-based communication. After several false starts, a confluence of advances now promises widespread commercial adoption. Gradient-based training deep spiking networks is an off-the-shelf technique for building general-purpose applications, with open-source tools underwritten theoretical results. Analog mixed-signal circuit designs are being replaced digital equivalents in newer simplifying application deployment while maintaining benefits. Designs in-memory computing also approaching maturity. Solving two key problems-how program general applications; how deploy them at scale-clears the way success processors. Ultra-low-power technology will find home battery-powered systems, local compute internet-of-things consumer wearables. Inspiration from uptake tensor processors GPUs can help field overcome remaining hurdles.

Language: Английский

Citations

0
Speck: A Smart event-based Vision Sensor with a low latency 327K Neuron Convolutional Neuronal Network Processing Pipeline DOI Creative Commons
Ole Richter, Yannan Xing, Michele De Marchi

et al.

arXiv (Cornell University), Journal Year: 2023, Volume and Issue: unknown

Published: Jan. 1, 2023

Edge computing solutions that enable the extraction of high-level information from a variety sensors is in increasingly high demand. This due to increasing number smart devices require sensory processing for their application on edge. To tackle this problem, we present vision sensor System Chip (SoC), featuring an event-based camera and low-power asynchronous spiking Convolutional Neural Network (sCNN) architecture embedded single chip. By combining both die, can lower unit production costs significantly. Moreover, simple end-to-end nature SoC facilitates small stand-alone applications as well functioning edge node larger systems. The event-driven delivers high-speed signals sparse data stream. reflected pipeline, which focuses optimising highly computation minimising latency 9 sCNN layers 3.36{\mu}s incoming event. Overall, results extremely low-latency visual pipeline deployed form factor with low energy budget cost. We architecture, individual blocks, principle benchmark against other capable processors.

Language: Английский

Citations

6
Gradient-descent hardware-aware training and deployment for mixed-signal neuromorphic processors DOI Creative Commons
Ugurcan Cakal, Maryada Maryada, Chenxi Wu

et al.

Neuromorphic Computing and Engineering, Journal Year: 2024, Volume and Issue: 4(1), P. 014011 - 014011

Published: Feb. 29, 2024

Abstract Mixed-signal neuromorphic processors provide extremely low-power operation for edge inference workloads, taking advantage of sparse asynchronous computation within spiking neural networks (SNNs). However, deploying robust applications to these devices is complicated by limited controllability over analog hardware parameters, as well unintended parameter and dynamical variations circuits due fabrication non-idealities. Here we demonstrate a novel methodology offline training deployment SNNs the mixed-signal processor DYNAP-SE2. Our applies gradient-based differentiable simulation device, coupled with an unsupervised weight quantization method optimize network’s parameters. Parameter noise injection during provides robustness effects device mismatch, making promising candidate real-world under constraints This work extends Rockpool, open-source deep-learning library SNNs, support accurate SNN dynamics. approach simplifies development process community, more accessible researchers developers.

Language: Английский

Citations

1
Integrating a hippocampus memory model into a neuromorphic robotic-arm for trajectory navigation DOI
Daniel Casanueva‐Morato,

Pablo López-Osorio,

Enrique Piñero-Fuentes

et al.

2022 IEEE International Symposium on Circuits and Systems (ISCAS), Journal Year: 2024, Volume and Issue: unknown, P. 1 - 5

Published: May 19, 2024

Language: Английский

Citations

1
A 4096 channel event-based multielectrode array with asynchronous outputs compatible with neuromorphic processors DOI Creative Commons
Matteo Cartiglia, Filippo Costa, Shyam Narayanan

et al.

Nature Communications, Journal Year: 2024, Volume and Issue: 15(1)

Published: Aug. 21, 2024

Bio-signal sensing is pivotal in medical bioelectronics. Traditional methods focus on high sampling rates, leading to large amounts of irrelevant data and energy consumption. We introduce a self-clocked microelectrode array (MEA) that digitizes bio-signals at the pixel level by encoding changes as asynchronous digital address-events only when they exceed threshold, significantly reducing off-chip transmission. This novel MEA comprises 64 × electrode array, an 2D-arbiter, Address-Event Representation (AER) communication block. Each operates autonomously, monitoring voltage fluctuations from cellular activity producing pulses for significant changes. Positive negative signal are encoded "up" "down" events routed via arbiter. present results chip characterization experimental measurements using electrogenic cells. Additionally, we interface mixed-signal neuromorphic processor, demonstrating prototype end-to-end event-based bio-signal processing. Developing efficient real-time closed-loop interfacing with processors challenge. The authors report GAIA sensor, which 4096-channel encodes biopotentials transmission power

Language: Английский

Citations

1
Evaluation of Dynamic Resource Allocation for Multi-Core ASICs DOI

Chetan Chaudhary,

Chandra Prakash Lora,

J Bhuvana

et al.

Published: Jan. 29, 2024

the demand for multiplied performance in included circuits has led to significant adoption of multi-center processors cutting-edge digital devices. To fully use potential those multi-core architectures, green and dynamic useful resource allocation is vital. This technical abstract info assessment techniques multi-middle application-precise incorporated (ASICs). In particular, point interest at exchange-off between energy such structures. The carried out by implementing a bendy configurable simulation framework, which permits easy evaluation different techniques. Essential procedures are considered worldwide highest quality static partitioning, deterministic aid allocation, probabilistic allocation. These techniques' overall strength efficiency evaluated across various benchmark programs. effects display that techniques, particularly approach, can considerably enhance decrease intake ASICs compared traditional partitioning.

Language: Английский

Citations

0