Mitigation of interfacial dielectric loss in aluminum-on-silicon superconducting qubits DOI Creative Commons
Janka Biznárová, Amr Osman, Emil Rehnman

et al.

arXiv (Cornell University), Journal Year: 2023, Volume and Issue: unknown

Published: Jan. 1, 2023

We demonstrate aluminum-on-silicon planar transmon qubits with time-averaged ${T_1}$ energy relaxation times of up to ${270\,\mu s}$, corresponding Q = 5 million, and a highest observed value ${501\,\mu s}$. use materials analysis techniques numerical simulations investigate the dominant sources loss, devise strategy towards mitigating them. The mitigation loss is achieved by reducing presence oxide, known host defects, near substrate-metal interface, growing aluminum films thicker than 300 nm. A coplanar-waveguide resonators shows that improvement owing reduction dielectric due two-level system defects. perform time-of-flight secondary ion mass spectrometry observe reduced oxygen at interface for films. correlation between enhanced performance film thickness tendency grow in columnar structures parallel grain boundaries, where size depends on thickness: transmission electron microscopy imaging has larger grains consequently fewer boundaries containing oxide this interface. These conclusions are supported different contributions device.

Language: Английский

Advanced CMOS manufacturing of superconducting qubits on 300 mm wafers DOI Creative Commons
Jacques Van Damme,

S. Massar,

R. Acharya

et al.

Nature, Journal Year: 2024, Volume and Issue: unknown

Published: Sept. 18, 2024

The development of superconducting qubit technology has shown great potential for the construction practical quantum computers

Language: Английский

Citations

8
Fast Universal Entangling Gate for Superconducting Quantum Computers DOI

M. AbuGhanem,

A. H. Homid, Ahmed S. Hendy

et al.

Published: Jan. 1, 2024

Universal quantum gates are crucial for efficient algorithm execution on computers, offering rapid and fault-tolerant manipulations. This paper presents a theoretical framework realizing novel entangling universal gate within the circuit electrodynamics (circuit QED) architecture. Our approach involves positioning two SQUIDs qubits resonant single-mode microwave cavity field, enabling implementation of SQSCZ gate, fusion square root SWAP ($\sqrt{SWAP}$) controlled-Z ($\sqrt{CZ}$) gates. serves as fundamental building block constructing including controlled-NOT Moreover, operates unitarily, ensuring logical reversibility, exhibits an power (EP) 1.5/9. Quantitative analysis reveals average fidelity $60\%$. To delve deeper into gate's performance, we conducted process tomography (QPT) by repeating experiment 11,000 times each measurement basis IBM Quantum's simulator. rigorous yielded remarkable $96.065616\%$. These findings offer promising implications future research applications.

Language: Английский

Citations

7
Mitigation of interfacial dielectric loss in aluminum-on-silicon superconducting qubits DOI Creative Commons
Janka Biznárová, Amr Osman, Emil Rehnman

et al.

npj Quantum Information, Journal Year: 2024, Volume and Issue: 10(1)

Published: Aug. 14, 2024

Abstract We demonstrate aluminum-on-silicon planar transmon qubits with time-averaged T 1 energy relaxation times of up to 270 μs, corresponding Q = 5 million, and a highest observed value 501 μs. Through materials analysis techniques numerical simulations we investigate the dominant source loss, devise strategy toward its mitigation. Growing aluminum films thicker than 300 nm reduces presence oxide, known host defects, near substrate-metal interface, as confirmed by time-of-flight secondary ion mass spectrometry. A loss coplanar waveguide resonators shows that this results in reduction dielectric due two-level system defects. The correlation between enhanced performance our devices film thickness is growth columnar structures parallel grain boundaries: transmission electron microscopy larger grains film, consequently fewer boundaries containing oxide interface.

Language: Английский

Citations

7
Signal Crosstalk in a Flip-Chip Quantum Processor DOI Creative Commons
Sandoko Kosen, Hang-Xi Li, Marcus Rommel

et al.

PRX Quantum, Journal Year: 2024, Volume and Issue: 5(3)

Published: Sept. 12, 2024

Quantum processors require a signal-delivery architecture with high addressability (low crosstalk) to ensure performance already at the scale of dozens qubits. Signal crosstalk causes inadvertent driving quantum gates, which will adversely affect gate fidelities in scaled-up devices. Here, we demonstrate packaged flip-chip superconducting signal-crosstalk competitive those reported other platforms. For capacitively coupled qubit-drive lines, find on-resonant better than −27 dB (average −37 dB). inductively magnetic-flux-drive less 0.13% direct-current flux 0.05%). These observed levels are adequately small and indicate decreasing trend increasing distance, is promising for further scaling up larger numbers We discuss implications our results design low-crosstalk on-chip architecture, including influence shielding tunnel structure, potential sources crosstalk, estimation crosstalk-induced qubit-gate error processors. Published by American Physical Society 2024

Language: Английский

Citations

5
Experimental error suppression in Cross-Resonance gates via multi-derivative pulse shaping DOI Creative Commons
Boxi Li, Tommaso Calarco, Felix Motzoi

et al.

npj Quantum Information, Journal Year: 2024, Volume and Issue: 10(1)

Published: July 2, 2024

Abstract While quantum circuits are reaching impressive widths in the hundreds of qubits, their depths have not been able to keep pace. In particular, cloud computing gates on multi-qubit, fixed-frequency superconducting chips continue hover around 1% error range, contrasting with progress seen carefully designed two-qubit chips, where rates pushed towards 0.1%. Despite strong impetus and a plethora research, experimental demonstration suppression these multi-qubit devices remains challenging, primarily due wide distribution qubit parameters demanding calibration process required for advanced control methods. Here, we achieve this goal, using simple method based multi-derivative, multi-constraint pulse shaping, which acts simultaneously against multiple sources. Our approach establishes two fourfold improvement default scheme, demonstrated four qubits IBM Quantum Platform limited intermittent access, enabling large-scale systems fully take advantage superior coherence times. The achieved CNOT fidelities 99.7(1)% those publically available come from both coherent accelerated gate time.

Language: Английский

Citations

4
Efficient frequency allocation for superconducting quantum processors using improved optimization techniques DOI
Zewen Zhang, Pranav Gokhale, Jeffrey Larson

et al.

Physical review. A/Physical review, A, Journal Year: 2025, Volume and Issue: 111(1)

Published: Jan. 17, 2025

Language: Английский

Citations

0
Integration of Through‐Sapphire Substrate Machining with Superconducting Quantum Processors DOI Creative Commons
Narendra Acharya, A. Robert Armstrong, Yashwanth Balaji

et al.

Advanced Materials, Journal Year: 2025, Volume and Issue: unknown

Published: Jan. 19, 2025

Abstract A sapphire machining process integrated with intermediate‐scale quantum processors is demonstrated. The allows through‐substrate electrical connections, necessary for low‐frequency mode‐mitigation, as well signal‐routing, which are vital computers scale in qubit number, and thus dimension. High‐coherence qubits required to build fault‐tolerant so material choices an important consideration when developing a technology platform. Sapphire, low‐loss dielectric substrate, has shown support high‐coherence qubits. In addition, recent advances such tantalum titanium‐nitride, both deposited on have demonstrated lifetimes exceeding 0.3 ms. However, the lack of any equivalent deep‐silicon etching create through‐substrate‐vias sapphire, or inductively shunt large dies, limited small‐scale processors, necessitates use chiplet architecture. Here, that compatible presented. This technique immediately provides means processing units (QPUs) route toward development through‐sapphire‐vias, allow advantages be leveraged facilitating sapphire‐compatible materials large‐scale QPUs.

Language: Английский

Citations

0
High kinetic inductance cavity arrays for compact band engineering and topology-based disorder meters DOI Creative Commons
Vincent Jouanny, Simone Frasca, Vera Jo Weibel

et al.

Nature Communications, Journal Year: 2025, Volume and Issue: 16(1)

Published: April 16, 2025

Abstract Superconducting microwave metamaterials offer enormous potential for quantum optics and information science, enabling the development of advanced technologies sensing amplification. In context circuit electrodynamics, such can be implemented as coupled cavity arrays (CCAs). continuous effort to miniaturize devices increasing scalability, minimizing footprint CCAs while preserving low disorder becomes paramount. this work, we present a compact CCA architecture using superconducting NbN thin films manifesting high kinetic inductance. The latter enables high-impedance (~1.5 kΩ), reducing resonator footprint. We demonstrate its versatility scalability by engineering one-dimensional with up 100 resonators structures that exhibit multiple bandgaps. Additionally, quantitatively investigate in symmetry-protected topological SSH edge modes, from which extract frequency scattering $$0.2{2}_{-0.03}^{+0.04}\%$$ 0.2 2 − 0.03 + 0.04 % . Our platform opens exciting prospects analog simulations many-body physics ultrastrongly emitters.

Language: Английский

Citations

0
Mitigating losses of superconducting qubits strongly coupled to defect modes DOI

Dante Colao Zanuz,

Quentin Ficheux, Laurent Michaud

et al.

Physical Review Applied, Journal Year: 2025, Volume and Issue: 23(4)

Published: April 24, 2025

Language: Английский

Citations

0
Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors DOI Creative Commons
Nandini Muthusubramanian, Matvey Finkel,

Pim Duivestein

et al.

Quantum Science and Technology, Journal Year: 2023, Volume and Issue: 9(2), P. 025006 - 025006

Published: Dec. 29, 2023

Abstract We investigate die-level and wafer-scale uniformity of Dolan-bridge bridgeless Manhattan-style Josephson junctions, using multiple substrates with without through-silicon vias (TSVs). Dolan junctions fabricated on planar have the highest yield lowest room-temperature conductance spread, equivalent to ∼ 100 M mathvariant="normal">H mathvariant="normal">z in transmon frequency. In TSV-integrated substrates, suffer most both disorder, making Manhattan preferable. show pronounced decrease from wafer center edge, which we qualitatively capture a geometric model spatially-dependent resist shadowing during junction electrode evaporation. Analysis actual overlap areas scanning electron micrographs supports model, further points remnant spatial dependence possibly due contact resistance.

Language: Английский

Citations

9