Improving Temporal Characteristics of Mealy FSM with Composite State Codes
Electronics,
Journal Year:
2025,
Volume and Issue:
14(7), P. 1406 - 1406
Published: March 31, 2025
In
this
paper,
we
proposed
a
new
state
assignment
method
focusing
on
Mealy
finite
machines
(FSMs).
The
makes
it
possible
to
improve
the
temporal
characteristics
of
circuits
FSMs,
internal
states
which
are
encoded
by
composite
codes
(CSCs).
These
consist
class
and
partial
codes.
Both
maximum
binary
We
propose
encode
classes
one-hot
main
goal
is
improving
value
FSM
cycle
time
without
any
significant
degradation
spatial
characteristics.
can
be
applied
if
implemented
using
look-up
table
(LUT)
elements
field-programmable
gate
arrays
(FPGAs).
resulting
circuit
includes
two
logic
blocks.
first
block
generates
input
memory
functions
outputs
depending
choice
allows
minimizing
systems
functions.
This
generating
most
single-LUT
circuits.
Some
require
dedicated
multiplexers.
second
final
values
outputs.
does
not
generate
functions,
case
CSC-based
FSMs.
approach
reducing
number
series-connected
LUTs
in
comparison
with
Due
reduction,
improved.
paper
an
example
synthesis
through
applying
method.
experiments
conducted
standard
benchmark
results
show
that
(by
average
9.15%).
relation
increases
10.03%,
power
consumption
7.63%.
Language: Английский
Transforming Group Codes in Mealy Finite State Machines with Composite State Codes
Applied Sciences,
Journal Year:
2025,
Volume and Issue:
15(8), P. 4289 - 4289
Published: April 13, 2025
A
new
state
assignment
method
focusing
on
Mealy
finite
machines
(FSMs)
is
proposed.
The
proposed
codes
are
an
alternative
to
composite
(CSCs).
CSCs
represented
as
concatenations
of
group
and
partial
codes.
Both
maximum
binary
We
propose
encoding
groups
using
one-hot
main
goal
this
improving
the
value
FSM
cycle
time
without
a
significant
degradation
spatial
characteristics.
can
be
applied
if
circuits
implemented
look-up
table
(LUT)
elements
field-programmable
gate
arrays
(FPGAs).
resulting
circuit
includes
three
logic
blocks.
first
block
generates
input
memory
functions
outputs
depending
assigned
in
way
minimizing
number
arguments
functions.
This
allows
for
generation
most
by
single-LUT
circuits.
second
final
values
outputs.
does
not
require
generate
functions,
CSC-based
FSMs.
third
transforms
into
their
equivalents.
approach
reduction
series-connected
LUTs
comparison
with
Due
reduction,
temporal
characteristics
improved.
paper
example
synthesis
applying
method.
experiments
were
conducted
standard
benchmark
results
show
that
allowed
improvement
average
8.81%.
Moreover,
relation
FSMs,
LUT
counts
decreased
4.00%.
Language: Английский