IEEE Transactions on Electron Devices, Journal Year: 2024, Volume and Issue: 71(8), P. 4670 - 4676
Published: Aug. 1, 2024
Language: Английский
IEEE Transactions on Electron Devices, Journal Year: 2024, Volume and Issue: 71(8), P. 4670 - 4676
Published: Aug. 1, 2024
Language: Английский
Nano Letters, Journal Year: 2024, Volume and Issue: 24(12), P. 3581 - 3589
Published: March 12, 2024
In this study, we demonstrate the implementation of programmable threshold logics using a 32 × memristor crossbar array. Thanks to forming-free characteristics obtained by annealing process, its accurate programming are presented 256-level grayscale image. By simultaneous subtraction between weighted sum and values with differential pair in an opposite way, 3-input 4-input Boolean implemented without additional reference bias. Also, verify full-adder circuit analyze fidelity, depending on device accuracy. Lastly, successfully implement 4-bit ripple carry adder achieve reliable operations read-based logic operations. Compared stateful driven switching, array can perform more reliably fewer steps thanks parallel operation.
Language: Английский
Citations
15Advanced Functional Materials, Journal Year: 2024, Volume and Issue: 34(36)
Published: May 14, 2024
Abstract 2D materials have garnered significant attention owing to their substantial potential across various applications, including thin‐film electronics, optoelectronics, and sensor devices, particularly, the synthesis deposition methods of are crucial. In this study, thin films tin disulfide (SnS 2 ), a layer‐structured metal dichalcogenide, deposited on an indium oxide (ITO) glass substrate through spin‐coating process prepare sandwich‐structured resistive switching (RS) device (ITO/SnS /ITO) by following magnetron sputtering ITO as top electrode. Notably, solution‐phased method provides efficient approach enhance performance ion doping. By incorporating calcium ions (Ca 2+ devices exhibit achieve outstanding synapse functionality. With DC sweep, on/off resistance ratio exceeding 100 can be sustained without degradation for up 5000 cycles. Furthermore, diverse synaptic functions, short‐term long‐term plasticity (STP, LTP) in both potentiation depression processes, spike‐timing‐dependent (STDP), paired‐pulse facilitation (PPF). The transition electrical function attributed migration doped Ca along grain boundary interlayer space SnS films.
Language: Английский
Citations
5Advanced Materials Technologies, Journal Year: 2024, Volume and Issue: 9(11)
Published: April 8, 2024
Abstract There is a need to design hardware synapse array appropriate for enhancing the efficiency of neuromorphic computing systems while minimizing energy consumption. This study introduces memristor device with an AlO x overshoot suppression layer (A‐OSL) achieve self‐compliance effect. By optimizing each cell within 16 × crossbar array, synaptic devices are successfully fabricated reliable characteristics and 3‐bit multilevel capabilities. In addition, oxygen composition TiO annealing conditions optimized reduce forming voltage minimize variation in switching voltage. As result, stable forming‐free obtained through A‐OSL insertion, reduction voltage, optimization. Also, target weights accurately transferred conducted inference process by applying spike signals following designated time step. The spiking neural network (SNN) demonstrated measuring vector‐matrix multiplication (VMM) array. VMM results exhibit classification accuracy 90.80% MNIST dataset, which close achieved software‐based approaches, amounting 91.85%.
Language: Английский
Citations
4Small, Journal Year: 2025, Volume and Issue: unknown
Published: Feb. 2, 2025
Adaptive learning capability of optoelectronic synaptic hardware holds promising application prospects in next generation artificial intelligence, and the development biometric retina perception is sternly hampered by three crucial issues, including well-balance between excitatory inhibitory, non-volatile multi-state storage, optimal energy consumption. In this work, a novel Cs2AgBiBr6/ZnO synapse proposed successfully programmed with optical electronic inhibitory light dual-mechanism: Lead-free perovskite Cs2AgBiBr6 guarantees abundant photogenerated carrier concentration, process capture release occurs ZnO layer, which can collaboratively modulate various plasticity behaviors depending on distinct stimulus. Consequently, multi-bit storage attained dual-mechanism memory (DNVM) as function consecutive spikes. The consumption DNVM 1.85 nJ at single spike, an ultra-low one 13.8 fJ triggered electrical pulse, approximatively meets requirement biological event performance further evaluated Pavlov's classical conditioning experiment visual system, offering exciting paradigm for implementing on-chip adaptive neuromorphic computing.
Language: Английский
Citations
0Journal of Alloys and Compounds, Journal Year: 2025, Volume and Issue: unknown, P. 180365 - 180365
Published: April 1, 2025
Language: Английский
Citations
0ACS Applied Materials & Interfaces, Journal Year: 2025, Volume and Issue: unknown
Published: May 13, 2025
Herein, a self-vanishing resistive random-access memory (RRAM) device is introduced utilizing cesium iodide (CsI) as the layer, with indium tin oxide and silver (Ag) electrodes. CsI-RRAM exhibits high ROFF/ON ratio (>106), stable data retention over 104 s, yield of functional devices. Electrical characterization confirms iodine vacancy-based filamentary switching, further validated by investigations into work function environmental influences. While devices exhibit excellent thermal stability, performance degradation under humidity effectively mitigated through PMMA encapsulation, enhancing their robustness. The reliably transitions between high-resistance (HRS) low-resistance states (LRS), demonstrating its functionality variable resistor during μ-LED illumination. Additionally, rapid dissolution CsI layer in deionized water within 90 s underscores potential technology, making it uniquely suited for transient applications. This exceptional combination performance, adaptability, properties establishes promising option destructible systems. are anticipated to play critical roles envisioned applications such military, security, intelligence sectors, where protecting sensitive information ensuring secure hardware disposal utmost importance.
Language: Английский
Citations
0Biomimetics, Journal Year: 2025, Volume and Issue: 10(5), P. 318 - 318
Published: May 15, 2025
In this study, we propose a neuromorphic computing system based on 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs). The approach leverages the velocity saturation effect in short-channel MOSFETs, which enables linear increase drain current with respect to gate voltage region. A NAND array TANOS (TiN/Al2O3/Si3N4/SiO2/poly-Si) stack was fabricated, and its electrical reliability characteristics were evaluated. Output of (L = 1 µm) long-channel 50 devices compared, confirming behavior due saturation. proposed system, WL serve as inputs, summed bitline (BL) currents represent outputs. Each synaptic weight is implemented using two paired devices, each layer corresponds fully connected (FC) layer, enabling efficient vector-matrix multiplication (VMM). MNIST pattern recognition conducted, demonstrated only 0.32% accuracy drop for device compared ideal case, 0.95% degradation under 0.5 V threshold variation, while maintaining robustness. These results highlight strong potential memory, offers high integration density technological maturity, applications.
Language: Английский
Citations
0Chaos Solitons & Fractals, Journal Year: 2024, Volume and Issue: 189, P. 115708 - 115708
Published: Nov. 11, 2024
Language: Английский
Citations
1Neural Networks, Journal Year: 2024, Volume and Issue: 176, P. 106355 - 106355
Published: April 30, 2024
Language: Английский
Citations
0Biomimetics, Journal Year: 2024, Volume and Issue: 9(6), P. 335 - 335
Published: May 31, 2024
To mimic the homeostatic functionality of biological neurons, a split-gate field-effect transistor (S-G FET) with charge trap layer is proposed within neuron circuit. By adjusting number charges trapped in Si3N4 layer, threshold voltage (Vth) S-G FET changes. prevent degradation gate dielectric due to program/erase pulses, gates for read operation and Vth control were separated through fin structure. A circuit that modulates width amplitude pulse was constructed generate Program/Erase as output circuit, firing rate can be lowered by increasing high rate. verify performance neural network based on FET, simulation online unsupervised learning classification 2-layer SNN performed. The results show recognition improved 8% fired.
Language: Английский
Citations
0