Binary and ternary compatible NAND/NOR logic-in-memory cell constructed with single-gated feedback field-effect transistors

Materials Science in Semiconductor Processing, Journal Year: 2025, Volume and Issue: 190, P. 109357 - 109357

Published: Feb. 2, 2025

Language: Английский

---

A 10.5 ppm/°C Modified Sub-1 V Bandgap in 28 nm CMOS Technology with Only Two Operating Points

Electronics, Journal Year: 2024, Volume and Issue: 13(6), P. 1011 - 1011

Published: March 7, 2024

Reference voltage/current generation is essential to the Analog circuit design. There have been several ways generate quality reference voltage using bandgap (BGR) and there are mainly two types: current mode mode. The current-mode (CBGR) widely accepted in industry due having an output which below 1 V. However, its drawbacks include a lack of proportional absolute temperature (PTAT) availability, large silicon area, multiple operating points, coefficient (TC). In this paper, various points explained detail with diagrams. Similar conventional (VBGR) circuits, modifications existing circuits only also proposed. Moreover, proposed BGR occupies much smaller area eliminating complimentary (CTAT) current-generating resistor. A new self-biased opamp was introduced operate from 1.05 V supply, reducing systematic offset TC BGR. solution has implemented 28 nm CMOS TSMC technology, extraction simulations were performed prove robustness circuit. targeted mean 500 mV, across industrial range (−40 125 °C), simulated approximately 10.5 ppm/°C. integrated noise within observable frequency band 19.6 µV (rms). 200-point Monte Carlo simulation displays histogram 2.6 mV accuracy 1.2% (±3-sigma). consumes 32.8 µW power supply fast process hot (125 °C) corner. It 81 × 42 µm (including capacitors). This design can aim for use biomedical sensor applications.

Language: Английский

---

Tri-state GNRFET-based fast and energy-efficient ternary multiplier

AEU - International Journal of Electronics and Communications, Journal Year: 2024, Volume and Issue: 177, P. 155239 - 155239

Published: March 26, 2024

Language: Английский

---

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Physica Scripta, Journal Year: 2024, Volume and Issue: 99(6), P. 065938 - 065938

Published: April 29, 2024

Abstract In this paper, a carbon nanotube field-effect transistor (CNTFET) based low power and robust ternary SRAM (TSRAM) cell with enhanced static noise margin (SNM) has been proposed. The proposed uses low-power core stack of 2 CNTFETs to discharge the read bit line (RBL) ground, unlike previous designs which use buffers or transmission gates (TG) alter voltage levels on RBL. TSRAM simulated relentlessly, using Stanford 32 nm CNTFET technology mode file Synopsis HSPICE tool under various operating conditions. Unlike other designs, cross-coupled inverters used as in show higher gain steep curves transition region mitigating cell. simulation results exhibit improvements performance parameters like consumption, energy, margins, reliability. At 0.9 V supply voltage, offers 52.44% 43.17% reduction write power, PDP 35.29% comparison, 36.36% improvement SNM compared best investigation. Also, design shows robustness designs.

Language: Английский

---

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Physica Scripta, Journal Year: 2024, Volume and Issue: 99(8), P. 085119 - 085119

Published: July 22, 2024

Abstract Multi-valued logic (MVL) extends binary by providing a framework to represent complex systems with more than two truth values. MVL was introduced confront the enormous interconnect issue associated in implementing presnt day nanoelectronic architectures. This paper delves into circuit design, computational aspects, and practical applications of quaternary system, which is type four The multi-threshold property carbon nanotube field-effect-transistors (CNTFETs), combined ability resistive random-access memory (RRAM) store multiple resistance values, has enabled design gates arithmetic circuits. A new CNTFET-based architecture been proposed implement compatible existing technologies. Quaternary such as inverter, NAND, NOR, circuits including decoder, half adder, multiplier have designed. power-delay-product (PDP) 62.38%, 93.4%, 80.29%, 14.79%, 20% less least PDP designs under consideration. static power reduction due effecciency high OFF state offered integrating RRAM explored.The subject various types parameter variations validate thir proper functionality presence these variations.

Language: Английский

---

Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Physica Scripta, Journal Year: 2024, Volume and Issue: 99(8), P. 085237 - 085237

Published: July 19, 2024

Abstract Recently, carbon nanotube field-effect transistors (CNTFETs) have garnered significant attention from VLSI engineers due to their exceptional electrical properties. This paper proposes a novel high-speed, low-power eight-transistor (8 T) static random-access memory (SRAM) cell based on 32-nm CNTFET technology. The SRAM was simulated using the HSPICE tool with V DD of 0.9 V. high-speed and characteristics design are attributed high subthreshold slope carrier mobility metal-oxide-semiconductor transistor (MOSFET)-like CNTFETs utilized in simulations. implementation dual threshold transistors, coupled transmission gate for bitline access, contributes enhanced performance. Key performance metrics such as noise margins, power consumption, delay, quality metric (SEQM) proposed been evaluated compared existing CNTFET-based designs. demonstrates reductions 73.73%, 43.18%, 58.70% read power, write hold respectively, lowest respective values other examined ranks second, third, second margin (WSNM), (HSNM), (RSNM), among Additionally, exhibits least sensitivity parametric variations SEQM, which provides comprehensive assessment access times, usage cell, has calculated. SEQM is 10.6, 1.89, 13.15, 1.82 times higher than that C6T, BLP8T, Mani’s 10 T, LP8T, respectively.

Language: Английский

---

Green Data Centers and Renewable Energy

Practice, progress, and proficiency in sustainability, Journal Year: 2024, Volume and Issue: unknown, P. 161 - 186

Published: July 26, 2024

Green data centers and renewable energy integration are essential for IT sustainability. Traditional consume more emit carbon as digital demand rises. prioritize resource efficiency, using energy-efficient technologies sources like sun, wind, hydropower. This minimizes environmental impact operational costs while promoting Innovative hardware cooling systems further reduce usage, setting a standard responsible computing. These can generate or purchase green power through solar panels wind turbines, aligning with global climate efforts. Collaboration between is crucial sustainable management, demonstrating balanced approach technical advancements responsibility, an example companies worldwide.

Language: Английский

---

Area-energy optimized ternary multiplier using efficient design approaches in GNRFET technology

AEU - International Journal of Electronics and Communications, Journal Year: 2024, Volume and Issue: 182, P. 155368 - 155368

Published: June 1, 2024

Language: Английский

---

An efficient design methodology for a tri-state multiplier circuit in carbon nanotube technology

Physica Scripta, Journal Year: 2024, Volume and Issue: 100(1), P. 015008 - 015008

Published: Dec. 4, 2024

Abstract This study delves into the computational aspects of ternary logic and use carbon nanotube field-effect transistors (CNTFETs) to develop an energy-efficient robust multiplier (TMUL). Leveraging exceptional qualities CNTFETs, such as balanced electron hole mobility easy modulation threshold voltage, research aims achieve desired designs. An innovative design method is employed, recommending a reduced count gates for achieving necessary levels. These are then utilized manage activation deactivation primary within TMUL cell convey intended logics outputs. Moreover, suggested focused on single- V DD , enhancing compatibility with goals multi-valued platform. The proposed circuit validated using Synopsis HSPICE simulator Stanford’s standard 32-nm CNTFET model file. Comparative analysis existing designs demonstrates 25.43% decrease in average power consumption, 42.24% reduction power-delay product (PDP), 24.69% energy-delay (EDP). undergoes thorough simulations under various conditions including load variations process, temperature (PVT) fluctuations confirm its reliability robustness.

Language: Английский

---

CNTFET-based SRAM cell design using INDEP technique

e-Prime - Advances in Electrical Engineering Electronics and Energy, Journal Year: 2024, Volume and Issue: 7, P. 100477 - 100477

Published: Feb. 22, 2024

As the size of transistor decreases in nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect (MOSFET). The carbon nanotube (CNTFET) has exhibited remarkable advantages compared MOSFETs circuit designs within range, owing its extraordinary characteristics. In this work, CNTFET-based six-transistor (6T) static random access memory (SRAM) is designed using low input-dependent (INDEP) technique. suggested circuits' performance efficiency enhanced CNTFET technology. design undergoes simulations 32 nm Stanford model. results obtained from indicate that INDEP 6T SRAM surpasses both conventional previous terms energy efficiency. hold, read, write operations use less power, hold take time complete. also demonstrates improved for read design. Furthermore, stability analysis conducted on noise margin (SNM) metric. approach comparison other schemes greater SNMs write, operations, indicating stability.

Language: Английский

---